description package schematic symbol features absolute maximum ratings symbol value units peak off-state voltage v drm 2000 v peak reverse voltage v rrm -5 v off-state rate of change of voltage immunity dv/ dt 1000 v/usec continuous anode current at 110 o c i a110 20 a repetitive peak anode current (pulse width=1usec) i asm 2000 a nonrepetitive peak anode current (pulse width=250nsec) i asm 4000 a rate of change of current di/ dt 20 ka/usec continuous gate-cathode voltage v gks +/-20 v peak gate-cathode voltage v gkm +/-25 v minimum negative gate-cathode voltage required for garanteed off-state v gk(off-min) -5 v maximum junction temperature t jm 150 o c maximum soldering temperature (installation) 260 o c this silicon power product is protected by one or more of the following u.s. patents: thinpak tm gate bond area gate return bond area anode bond area opposite side cathode bond area 5,446,316 5,557,656 5,564,226 5,517,058 4,814,283 5,135,890 5,521,436 5,585,310 5,248,901 5,366,932 5,497,013 5,532,635 5,105,536 5,777,346 5,446,316 5,577,656 5,473,193 5,166,773 5,209,390 5,139,972 5,103,290 5,028,987 5,304,847 5,569,957 4,958,211 5,111,268 5,260,590 5,350,935 5,640,300 5,184,206 5,206,186 5,757,036 5,777,346 5,995,349 4,801,985 4,476,671 4,857,983 4,888,627 4,912,541 5,424,563 5,399,892 5,468,668 5,082,795 4,980,741 4,941,026 4,927,772 4,739,387 4,648,174 4,644,637 4,374,389 4,750,666 4,429,011 5,293,070 this voltage controlled solidtron (vcs) discharge switch utilizes an n-type mos-controlled thyristor mounted on a thinpak tm , ceramic "chip-scale" hybrid. the vcs features the high peak current capability and low on- state voltage drop common to scr thyristors combined with extremely high di/dt capability. this semiconductor is intended for the control of high power circuits with the use of very small amounts of input energy and is ideally suited for capacitor discharge applications. the thinpak tm package is a perforated, metalized ceramic substrate attached to the silicon using 302 o c solder. an epoxy underfill is applied to protect the high voltage termination from debris. all exterior metal surfaces are tinned with 63pb/37sn solder providing the user with a circuit ready part. it's small size and low profile make it extremely attractive to high di/dt applications where stray series inductance must be kept to a minimum. l 2000v peak off-state voltage l 20a continuous rating l 4ka surge current capability l high di/dt capability l low on-state voltage l mos gated control l low inductance package anode (a) gate (g) cathode (k) gate return (gr) preliminary data sheet - product status : first production : this data sheet contains preliminary data . supplementary data will be published at a later date. silicon power reserves the right to make changes at any time without notice. advanced pulse power device n-mos vcs , thinpak tm preliminary data sheet smct ta20n20a10
performance characteristics t j =25 o c unless otherwise specified measurements parameters symbol test conditions min. typ. max. units anode to cathode breakdown voltage v (br) v gk =-5, i a =1ma 2000 v anode-cathode off-state current i d v gk =-5v, v ak =2000v t c =25 o c <10 100 ua t c =150 o c 250 1000 ua gate-cathode turn-on threshold voltage v gk(th) v ak =v gk , i ak =1ma 0.7 v gate-cathode leakage current i gk(lkg) v gk =+/-20v 500 na anode-cathode on-state voltage v t i t =25a, v gk =+5v t c =25 o c 2.4 3.0 v t c =150 o c 3 3.5 v input capacitance c iss 5 nf turn-on delay time t d(on) 0.2uf capacitor discharge 230 300 ns rate of change of current di/ dt t j =25 o c, v gk = -5v to +5v 18 ka/usec peak anode current i p v ak =1400v, rg=4.7 w 2200 a discharge event energy e dis l s = 15nh 196 mj turn-on delay time t d(on) 0.2uf capacitor discharge 180 250 ns rate of change of current di/ dt t j =25 o c, v gk = -5v to +5v 28 ka/usec peak anode current i p v ak =1800v, rg=4.7 w 3300 a discharge event energy e dis l s = 15nh 310 mj junction to case thermal resistance r q jc anode (bottom) side cooled (note 1.) 0.09 o c/w junction to case thermal resistance r q jc cathode-gate (top) side cooled (note 2.) 1.6 o c/w notes: 1. case exterior assumed to be 0.002" of 63sn/37pb solder applied directly to anode. 2. case exterior assummed to be 0.002" of 63sn/37pb solder applied directly to cathode bond area of thinpak. typical performance curves (unless otherwise specified) typical performance curves figure 1. on-state characteristics figure 2. on-state characteristics figure 3. predicted high current on-state characteristics 0 25 50 75 100 125 150 0.0 2.0 4.0 6.0 8.0 10.0 v t - on-state voltage=volts i t - on-state current-a v gk =+5v pulse duration = 250usec. duty cycle=<0.5% t j =25 o c t j =150 o c t j =85 o c 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v t - on-state voltage=volts i t - on-state current-a v gk =+5v pulse duration = 250usec. duty cycle=<0.5% t j =25 o c t j =150 o c t j =85 o c 0 500 1000 1500 2000 2500 3000 3500 4000 0 20 40 60 80 100 120 140 160 180 200 220 v t - on-state voltage - v i t - on-state current-a t j =25 o c r on = 30m w t j =150 o c r on = 54m w t j =85 o c r on = 39m w advanced pulse power device n-mos vcs , thinpak tm preliminary data sheet smct ta20n20a10
typical performance curves (continued) figure 4. turn-on delay characteristics with l s = 15nh, 25nh and 50nh figure 5. peak anode current vs. anode supply voltage (see figure 7.) figure 6. discharge energy vs. anode supply voltage (see figure 7.) 100 150 200 250 300 350 400 450 600 800 1000 1200 1400 1600 1800 2000 v cc - collector (anode) supply voltage-volts t d(on)i - turn-on delay-nsec t j =25 o c c=0.2uf r g =4.7 w v gk =-5v to +5v l s =15nh l s =25nh l s =50nh 500 1,000 1,500 2,000 2,500 3,000 3,500 4,000 600 800 1000 1200 1400 1600 1800 2000 v cc - collector (anode) supply voltage - v i p - peak anode current - a l s =15nh l s =25nh l s =50nh t j =25 o c c=0.2uf r g =4.7 w v gk =-5v to +5v 25 75 125 175 225 275 325 375 600 800 1000 1200 1400 1600 1800 2000 v cc - collector (anode) supply voltage - v e dis - discharge event energy - mj t j =25 o c c=0.2uf r g =4.7 w v gk =-5v to +5v l s =15nh l s =25nh l s =50nh advanced pulse power device n-mos vcs , thinpak tm preliminary data sheet smct ta20n20a10
typical performance curves (continued) figure 7. 0.2uf pulsed discharge circuit and waveforms application notes packaging and handling figure 8. package dimensions a1. use of gate return bond area. the vcs was designed for high di/dt applications. an independent cathode connection or "gate return bond area" was provided to minimize the effects of rapidly changing anode-cathode current on the gate control voltage, (v=l*di/dt). it is therefore, critcal that the user utilize the gate return bond area as the point at which the gate driver reference (return) is attached to the vcs device. 1. all metal surfaces are tinned using 63pb/37sn solder. 2. installation reflow temperature should not exceed 260 o c or internal package degradation may result. 3. package may be cooled from either top or bottom. 4. as with all mos gated devices, proper handling procedures must be observed to prevent electrostatic discharge which may result in permanent damage to the gate of the device v gk v ak i a i p t d(on) 0 ref. 0 ref. 90% 10% di/dt - 10% to 50% of i a l the waveform shown is representative of one produced using a very low inductance circuit (<10nh) and a smctta32n14a10 mct. smct ta20n20a10 devices do not produce ringing waveforms l v gk is held positive until i a oscillations have ended ( i a =0). supply voltage l series (total) dut r sense = 0.010 w c=0.2uf + - r g gate driver +5v -5v l l series(total) is caculated using 1 / (f 2 p ) 2 c where f = frequency of i a when using smct ta32n14a10 for circuit set up and calibration. l r sense is a calibrated current viewing resistor (cvr) .042 thick advanced pulse power device n-mos vcs , thinpak tm preliminary data sheet smct ta20n20a10
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